The present invention relates to a method for fabricating a semiconductor device; and more particularly, to a flash memory device with a dielectric layer having a high k-dielectric constant and a method for fabricating the same.
When using a conventional oxide-nitride-oxide (ONO) structure as a dielectric structure (i.e., an inter-poly oxide (IPO) layer or an inter-poly dielectric (IPD) layer) existing between a floating gate (FG) and a control gate (CG), a distance between devices decreases as the integration scale of semiconductor devices improves. Accordingly, it becomes difficult to perform a gap-filling process and thus, the devices are often hardly isolated.
Furthermore, as a size of the device has been reduced, a property of a capacitor for storing electric charges may be degraded. Accordingly, a high k-dielectric thin layer having a small thickness and a high k-dielectric constant is used as the IPO layer or the IPD layer.
Recently, a process of using a high k-dielectric thin layer with an OZO structure, formed by sequentially stacking an oxide layer, a zirconium oxide (ZrO2) layer and an oxide layer has been suggested to overcome the aforementioned limitations.
FIG. 1 is a cross-sectional view illustrating a conventional flash memory device.
A tunnel oxide layer 12 is formed over a substrate 11, and a floating gate 13 is formed over the tunnel oxide layer 12. A dielectric structure 14 is formed over the floating gate 13. The dielectric structure 14 is formed by sequentially stacking a first silicon oxide (SiO2) layer 14A, a zirconium oxide (ZrO2) layer 14B, and a second silicon oxide (SiO2) layer 14C. A control gate 15 is formed over the dielectric structure 14.
However, in the case of using the ZrO2 layer, the ZrO2 layer may be crystallized at a predetermined thickness or greater while forming a thin layer. Accordingly, along a grain boundary, current is likely to leak or a defect may be generated. As a result, device reliability may be degraded.